SVC is not permitted on this architecture
Bug #1449610 reported by
cfriedt
This bug affects 1 person
Affects | Status | Importance | Assigned to | Milestone | |
---|---|---|---|---|---|
GNU Arm Embedded Toolchain |
New
|
Undecided
|
Unassigned |
Bug Description
The spec clearly states in section A6.7.68 that SVC is, indeed, permitted.
https:/
pre-processed asm:
.text; .align 0; .globl _foo; .thumb; .syntax unified; .type _foo,#function; _foo: .fnstart;
mov lr, r2
ldr r7, =(0 + 91)
svc #0
mov r0, lr
ldr r7, =(0 + 1)
svc #0
mov r0, #0
ldr r0, [r0]
.fnend; .size _foo, .-_foo;
Assembler messages:
Error: SVC is not permitted on this architecture
Error: SVC is not permitted on this architecture
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I believe this is "solved" by specifying "-march=armv6s-m -mthumb" rather than "-march=armv6-m -mthumb", although the presence or lack of presence of an operating system should have little sway over what instructions are "permitted" to be generated by the assembler.
The concept of permission to generate an instruction is a completely unnecessary obstacle that is not specified by ARM, afaik. Therefore, this problem should not have to be "solved" in the first place.
Corollary via inconsistence: why would "-march=armv7-m" enable the assembler to always be "permitted" to generate svc?