wily: arm64: irqbalance works at oneshot mode at default
Bug #1476512 reported by
Ming Lei
This bug affects 1 person
| Affects | Status | Importance | Assigned to | Milestone | |
|---|---|---|---|---|---|
| irqbalance (Ubuntu) |
New
|
Undecided
|
Unassigned | ||
Bug Description
From kernel v4.0, CPU cache topo information is added into sysfs for ARM64, in which all cores often share one L3 cache
such as APM xgene, so cache domain count can be one, and irqbalance will work at oneshot mode.
With the following upstream patch, irqbalance can work as before.
https:/
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