Comment 3 for bug 1702499

Greetings,

I have a question for you. Why do you want your ISR function to be naked?

The contemporary ARM cores, and to be fair I only know the Cortex-M cores well enough to be sure, don't need special handling for ISRs. The standard compiler preamble is acceptable. In fact, I think that the core is responsible for register save and restore.

The ARM documentation for exception handling on the Cortex M3 (which I cannot link here as the ARM documentation doesn't provide direct URL access to the documentation) states that

'When the processor takes an exception, unless the exception is a tail-chained or a late-arriving exception, the processor pushes information onto the current stack. This operation is referred to as stacking and the structure of eight data words is referred as the stack frame. The stack frame contains the following information:'

So, the question is this. What core are you using that requires you to manually manage the stack in an exception handler?

Cheers