Comment 8 for bug 579337

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regarding GPSim, there's another thing to take into consideration: for quite a while, those folks have been trying to add support for emulating multiple targets/CPUs simultaneously, however their architecture turned out not to be flexible enough to allow for this to happen. While I am certainly not proposing to implement anything like that within the forseeable future, it would definitively be a good idea to keep such a facility in mind, so that the design and architecture could be generic enough to eventually help implementing something like that.

Also, regarding the XML format: instruction effects would need to be fully described as well, side-effects may depend on instruction arguments and may affect various/arbitrary other processor components (registers, flags, ports, stack) this would require exposing parameter arguments via standard names, so that the following markup may easily refer to each instruction argument, for example:

<mnemonic name="MVI" description="move immediate">
  <parameters number="1">
   <param type="immediate" size="8">
     <effect type="ASSIGN_BYTE:imm->reg" val="$param1" target="reg:A"/>
   </param>

  </parameters>
</mnemonic>